Category Archives: Uncategorized

 Vic and Jack attended a national VLSI competition in Beijing and got third prize. Hope we can win a better prize in the next year.

Our paper  “Towards Practical Code Based Signature: Implementing Fast and Compact QC-LDGM Signature Scheme on Embedded Hardware”  has been accepted for publication in the IEEE Transactions on Circuits and Systems I.

Our paper “Spectral Arithmetic in Montgomery Modular Multiplication” has been accepted for publication in the Journal of Cryptographic Engineering.

Our paper “Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication” has been accepted for publication in the IEEE Transactions on Computers.

Our paper  “Compact Constant Weight Coding Engines for the Code Based Cryptography”  has been accepted for publication in the IEEE Transactions on Circuits and Systems II.

Our paper  “Area-Time Efficient Computation of Niederreiter Encryption on QC-MDPC Codes for Embedded Hardware”  has been accepted for publication in the IEEE Transactions on Computers.

Our paper  “A Fully Pipelined Hardware Architecture for Intra Prediction of HEVC”  has been accepted for publication on IEEE Transactions on Circuits and Systems for Video Technology.  In this work, we proposed multiple techniques for the hardware architecture for intra prediction … Continue reading →

Our CALAS group has recieved a RGC grant of over 6 million HKD. The proposal title of this project is “Efficient Algorithms and Hardware Accelerators for Tensor Decomposition and Their Applications to Multidimensional Data Analysis”. Dr. Cheung is a Co-PI … Continue reading →

Our paper  “Parameter space for the architecture of FFT-based Montgomery modular multiplication”  has been accepted for publication in the IEEE Transactions on Computers.  In this paper, a systematic parameter selection method is proposed for efficient FFT-based Montgomery modular multiplication implementation. The … Continue reading →

Our paper  “Fast and Generic Inversion Architectures over GF(2m) Using Modified Itoh-Tsujii Algorithms”  has been accepted for publication in the IEEE Transactions on Circuits and Systems II. We have proposed in this paper two novel architectures for multiplicative inverse over GF(2^m), … Continue reading →