CALAS Seminar Series

If you are interested in the upcoming or future seminars, please contact us for more information.

GPU Acceleration for Word-Wise Homomorphic Encryption

Speaker: Dr. Hao YANG, PhD Scholar Nanjing University of Aeronautics and Astronautics

Date/Time: May 20th 2024 (Thur) at 10:00 HKT

Abstract: (Fully) Homomorphic Encryption (HE) is a promising privacy-enhancing cryptographic technique that allows computations to be performed on encrypted data without the need for decryption, and it has potentially wide applications across various industries. However, the primary challenge faced by HE is its low performance. The GPU, a powerful accelerator not only for Al tasks but also for cryptographic computations, is explored to accelerate HE in this context. This presentation first provides a brief overview of HE and its applications, then delves into the implementation details of HE. We explore several optimizations for both low-level arithmetic and high-level homomorphic operations on GPUs. Building on these foundations, we introduce an open-sourced GPU library specifically for word-wise HE schemes, named Phantom FHE. Finally, some potential directions for future research are discussed.

Biography: Hao YANG completed his bachelor’s and PhD degrees from Nanjing University of Aeronautics and Astronautics in 2019 and 2024respectively. His research focuses on lattice-based cryptography, fully homomorphic encryption, and GPU acceleration. He has published in journals including IEEE TIFS, IEEE TDSC, and lEEE TC. He has participated in more than 5 national projects from NSFC and MOST. He has also participated as a main contributor in projects funded by Ant Group and Huawei.

Sensor Location Optimization for Effective and Robust Beamforming

Speaker: Dr. Wei LIU, Reader, Queen Mary University of London, IEEE AESS Distinguished Lecturer

Date/Time: May 16th 2024 (Thur) at 16:00 HKT

Abstract: In many applications, the sensor array’s geometrical layout is assumed to be fixed and given in advance. However, it is possible to change the geometrical layout of the array including adjacent sensor spacing and these additional spatial degrees of freedom (DOFs) can be exploited to improve the performance in terms of either beamforming direction finding, or both. With the development of compressive sensing (CS) or the sparsity maximization framework, a new CS-based framework with a theoretically optimum solution (due to the convex nature of the formulation) has been developed for general sensor location optimization, with robustness against various array model errors considered too. In this talk, the CS-based framework for sensor location optimization will be presented for effective and robust beamforming, general introduction to both narrowband beamforming and broadband/wideband beamforming.

Biography: Dr. Wei LIU received his BSc in Space Physics (minor in Electronics) in 1996 and LLB in Intellectual Property Law in 1997 from Peking University, China, MPhil from the Department of Electrical and Electronic Engineering, University of Hong Kong, in 2001, PhD in 2003 from the School of Electronics and Computer Science, University of Southampton, U.K. Since September 2023, he has been a Reader at the School of Electronic Engineering and Computer Science, Queen Mary University of London. His research interests cover a wide range of topics in signal processing, with a focus on array signal processing (beamforming and source separation/extraction, the direction of arrival estimation, target tracking, and localization, etc.), and its various applications.

 

Revealing the Weakness of Addition Chain-based Masked SBox
Implementations

Speaker: Dr. Jingdian MING, Doctoral Researcher, Jiaxing Research Institute, Zhejiang University

Date/Time: May 14th 2024 (Tue) at 9:00 HKT

Abstract: Addition chain is a well-known approach for implementing higher-order masked SBoxes. However, this approach induces more computations of intermediate monomials, which in turn leaks more information related to the sensitive variables and may consequently decrease its side-channel resistance. Thus, we investigate the resilience of monomial computations with respect to side-channel analysis. We select several representative addition chain implementations, based on their theoretical resilience, that demonstrate the strongest and weakest resistance to side-channel analysis. In practical experiments based on an ARM Cortex-M4 architecture, we collect power and electromagnetic traces, considering different noise levels. The results reveal that the weakest masked SBox implementation exhibits a side-channel resistance nearly identical to an unprotected implementation. Moreover, we find that some monomials with smaller output size leak more sensitive information than the SBox output. This finding applies to various other masking schemes, including inner product masking.

Biography: Jingdian MING received the Ph.D. degree in 2022 from the School of Cyber Security, University of Chinese Academy of Sciences. He is currently an Associate Researcher at Jiaxing Research Institute, Zhejiang University. His main research interests include hardware security, cryptographic engineering, and side-channel analysis. Over the years, he has published multiple papers in hardware security, including TIFS, TCHES, and DATE.

 

Applications, Tools and Outlook for Reconfigurable Computing:
Selected Musings

Speaker: Prof. Andreas KOCH, Professor, Technische Universität Darmstadt

Date/Time: Apr 10th 2024 (Wed) at 16:00 HKT

Abstract: With recent improvements in silicon fabrication technology, reconfigurable devices can now be applied to accelerate functions beyond the traditional computing domains. In-network processing and smart computational storage are just two of these approaches. We discuss both simple and more complex application examples for both of these domains, covering a networkattached ML inference appliance, a JOIN accelerator for distributed databases, and also look forward to using a cache-coherent interconnect, such as CCIX or CXL, to tackle a complex database acceleration scenario linking a computational storage unit using near-data processing to a full-scale PostgreSQL database system. Beyond these hardware architectures, the talk also examines improvements in programming tools specialized for the realization of reconfigurable computing systems. Using the open-source TaPaSCo framework as an example, advanced features such as on-chip dynamic parallelism, flexibly customizable inter-processing element communications, and host/accelerator shared virtual memory with physical page migration capabilities are discussed.

Biography: Prof. Andreas KOCH is a full professor at TU Darmstadt in Germany, where he leads the Embedded Systems and Applications Group. He has been working on accelerated computing since the early 1990s, mainly using reconfigurable devices such as FPGAs and CGRAs, but also considering GPUs and specialized ML accelerators. He has always “played on both sides of the fence”, performing research not only on hardware architectures, but also on the software tools and libraries required to exploit them. Among others, he is currently applying his expertise to the domains of storage acceleration, near-data and in-network processing as well as ML inference for sum-product networks.

 

Efficient Programming on Heterogeneous Accelerators forSustainable Computing

Speaker:  Prof. Peipei ZHOU, Assistant ProfessorDepartment of Electrical and Computer Engineering, University of Pittsburgh

Date/Time: Mar 18th 2024 (Mon) at 9:00 HKT

Abstract:  There is a growing call for increasingly agile computational power for edge and cloud infrastructure to serve the computationally complex needs of ubiquitous computing devices. One important challenge is addressing the holistic environmental impacts of these next-generation computing systems. A life-cycle view of sustainability for computing systems is necessary to reduce environmental impacts such as greenhouse gas emissions from these computing systems in different phases: manufacturing, operational, and disposal/recycling. My research investigates how to efficiently program and map widely used workloads on heterogeneous accelerators and seamlessly integrate them with existing computing systems towards sustainable computing. In this talk, I will first discuss how new mapping solutions, i.e., composing heterogeneous accelerators within system-on-chip with both FPGAs and AI tensor cores, achieve orders of magnitude energy efficiency gains when compared to monolithic accelerator mapping designs for various applications, including deep learning, security, and others. Then, I will apply such novel mapping solutions to show how design space explorations are performed when composing heterogeneous accelerators in latency-through tradeoff analysis. I will further discuss how such mapping and scheduling can be applied to other computing systems, such as GPUs, to improve energy efficiency and, therefore, reduce the operational carbon cost. Finally, I will introduce the REFRESH FPGA chiplets, explain why REFRESH chiplets help reduce the embodied carbon cost, and discuss the challenges and opportunities.

Biography: Prof. Peipei ZHOU is a tenure-track assistant professor in the Department of Electrical Computer Engineering at the University of Pittsburgh. She received her Ph.D. in Computer Science (2019) and M.S. in Electrical and Computer Engineering (2014) from UCLA, and her B.S. in Electrical and Computer Engineering (2012) from Southeast University. Her research investigates architecture, programming abstraction, and design automation tools for reconfigurable computing and heterogeneous computing. She has published 30 papers in IEEE/ACM computer system and design automation conferences and journals including FPGA, FCCM, DAC, ICCAD, ISPASS, TCAD, TODAES, TECS, IEEE Micro, etc. Her work has won the 2019 IEEE TCAD Donald O. Pederson Best Paper Award. Other awards include the 2023 ACM/IEEE IGSC Best Viewpoint Paper Finalist, the 2018 IEEE ISPASS Best Paper Nominee, and the 2018 IEEE/ACM ICCAD Best Paper Nominee.

 

Fast Deep Learning for Scientific Applications with FPGAs

Speaker:  Dr. Zhiqiang QUE, Research Associate Department of Computing, Imperial College London

Date/Time: Mar 13th 2024 (Wed) at 16:00 HKT

Abstract: In the domain of scientific research, particularly in fields like particle physics, the demand for rapid data acquisition and in- situ processing systems is critical. These systems rely on custom processing elements with very low latency and high data bandwidth, along with real-time control modules. Integrating real-time machine learning algorithms with these processes can enable advances in scientific discovery. A critical component of such integrations is the acceleration of deep learning inference using reconfigurable accelerators such as FPGAs, which enables sophisticated processing in real-time with superior accuracy. In this talk, I first describe the FPGA-based fast Graph Neural Networks (GNNs) tailored for particle physics applications, demonstrating our achievements in minimizing latency and maximizing throughput. I then present our new studies on automation of optimizations for Fast Deep Learning (FastDL) in scientific applications.

Biography: Dr. Zhiqiang QUE is a research associate in the Custom Computing Research Group in the Department of Computing at Imperial College London. His experience includes ARM CPU design at Marvell Semiconductor (2011-2015) and Low Latency FPGA systems at CFFEX (2015-2018). He earned his PhD under Prof. Wayne LUK at Imperial College in 2023, while completing his B.S. and M.S. at Shanghai Jiao Tong University in 2008 and 2011. His research focuses on computer architecture, embedded systems, high-performance computing, and design automation for hardware optimization.

 

Intelligent Digital Design and Implementation with Machine Learning in EDA

Speaker:  Prof. Zhiyao XIE, Assistant Professor Department of Electronic and Computer Engineering Hong Kong University of Science and Technology

Date/Time: Feb 1st 2024 (Thu) at 14:00 HKT

Abstract: As the integrated circuit (IC) complexity keeps increasing, the chip design cost is skyrocketing. There is a compelling need for design efficiency improvement through new electronic design automation (EDA) techniques. In this talk, I will present multiple design automation techniques based on machine learning (ML) methods, whose major strength is to explore highly complex correlations based on prior circuit data. These techniques cover various chip-design objectives and design stages, including layout, netlist, register-transfer level (RTL), and micro-architectural level. I will focus on the different challenges in design objective prediction at different stages, and present our customized solutions. In addition, I will share our latest observations in design generation with large language models.

Biography: Prof. Zhiyao XIE is an Assistant Professor in the Department of Electronic and Computer Engineering (ECE) at Hong Kong University of Science and Technology. He received his Ph.D. in 2022 from Duke University. His research focuses on electronic design automation (EDA) and machine learning for VLSI design. Prof. XIE has received multiple prestigious awards, including the UGC Early Career Award 2023, ACM Outstanding Dissertation Award in EDA 2023, EDAA Outstanding Dissertation Award 2023, MICRO 2021 Best Paper Award, ASP-DAC 2023 Best Paper Award, ACM SIGDA SRF Best Poster Award 2022, etc. During his Ph.D. studies, Prof. XIE also worked as a research intern at Nvidia, Arm, Cadence, and Synopsys. Prof. Zhiyao XIE, Assistant Professor Department of Electronic and Computer Engineering Hong Kong University of Science and Technology

 

SoftwareProgrammable AcceleratorCentric Systems

Speaker:  Dr. Zhenman Fang, Assistant Professor, Computer EngineeringSimon Fraser University

Date/Time: Nov 15th 2023 (Wed) at 10:00 HKT

Abstract: With the end of CPU scaling due to dark silicon limitations, customizable hardware accelerators on FPGAs have gained increasing attention in modern datacenters and edge devices due to their low power, high performance and energy-efficiency. Evidenced by Microsoft’s FPGA deployment in its Bing search engine and Azure cloud, the public cloud access by Amazon and Alibaba, Intel’s US$16.7B acquisition of Altera, and AMD’s US$50B acquisition of Xilinx, FPGA-based customizable acceleration is considered one of the most promising approaches to sustain the ever-increasing performance and energy-efficiency demand of emerging application domains such as machine learning and big data analytics. In this talk, Dr. Fang will first explain how FPGA hardware accelerators achieve amazing improvements and give an overview of our research on software- programmable accelerator-centric systems [PIEEE 2019, TRETS 2021]. Following that, he will present a few successful case studies on software-defined hardware acceleration for machine learning and big data analytics, including 1) Caffeine for early-day CNN acceleration [TCAD 2019 best paper], 2) HeatViT for vision transformer pruning and acceleration [HPCA 2023], 3) CHIP-KNN for k-nearest neighbors acceleration [FPT 2020, TRETS 2023], and 4) SQL2FPGA for compiling Spark SQL onto FPGAs [FCCM 2023]

Biography: Dr. Zhenman Fang is a Tenure-Track Assistant Professor in School of Engineering Science, Computer Engineering Option, Simon Fraser University, Canada, where he founded and directs the HiAccel lab. His recent research focuses on customizable computing with specialized hardware acceleration, which aims to sustain the ever-increasing performance, energy-efficiency, and reliability demand of important application domains in post- Moore’s law era. It spans the entire computing stack, including emerging application characterization and acceleration (including machine learning, computational genomics, big data analytics, and high-performance computing), novel accelerator-rich and near-data computing architecture designs, and corresponding programming, runtime, and tool support. Dr. Fang has published over 50 papers in top conferences and journals and two US patents, including two best paper awards (TCAD 2019 Donald O. Pederson best paper award and MEMSYS 2017), two best paper nominees (HPCA 2017 and ISPASS 2018), and an invited paper from Proceedings of the IEEE 2019. His research has also been recognized with a NSERC (Natural Sciences and Engineering Research Council of Canada) Alliance Award (2020), a CFI JELF (Canada Foundation for Innovation John R. Evans Leaders Fund) Award (2019), a Xilinx University Program Award (2019), a Team Award from Xilinx Software and IP Group (2018), and a Postdoc Fellowship from UCLA Institute for Digital Research and Education (2016-2017). More details can be found in his personal website: https://www.sfu.ca/~zhenman/.

 

Design and Implementation of Lightweight PostQuantum Cryptography: From Algorithmic Derivation to Architectural Innovation

Speaker:  Dr. Jiafeng (Harvest) XIE, Assistant Professor Department of Electrical and Computer Engineering, Villanova University

Date/Time: Oct 18th 2023 (Wed) at 16:00 HKT

Abstract: Post-quantum cryptography (PQC) has recently drawn significant attention from various communities, along with the rapid advancement in building large-scale quantum computers. Apart from the National Institute of Standards and Technology (NIST) PQC standardization process targeting general-purpose algorithms, the research community is also looking for lightweight PQC for specific applications. In this talk, I will follow this trend to introduce the design and implementation of a promising lightweight PQC, the Ring-Binary-Learning-with-Errors (RBLWE)-based encryption scheme. Specifically, this talk stands from the hardware implementation perspective, covering algorithmic derivation and architectural innovation. A series of novel algorithms and architectures will be covered in this talk. I hope that this talk will attract more research on the lightweight PQC development and further possible standardization.

Biography: Dr. XIE is currently an Assistant Professor in the Department of Electrical and Computer Engineering, Villanova University. His research interests include cryptographic engineering, hardware security, post-quantum cryptography, and digital design for large-scale computing systems. Dr. Xie has served as technical committee member for many reputed conferences such as HOST, ICCAD, and DAC. He is also currently serving as Associate Editor for IEEE Transactions on VLSI Systems, Microelectronics Journal, and IEEE Access. He also will be serving as Associate Editor for IEEE Transactions on Circuits and Systems-II starting 2024. He received the IEEE Access Outstanding Associate Editor for the year of 2019. He also received the 2022 IEEE Philadelphia Section Merrill Buckley Jr. Student Project Award and the Best Paper Award from IEEE International Symposium on Hardware Oriented Security and Trust 2019 (HOST’19).

 

6G, Metaverse, and Generative AI: From Convergence to Emergence

Speaker:  Prof. Martin Maier, Full Professor, Institut National de la Recherche Scientifique

Date/Time: Oct 12th (Thursday) at 16:00 HKT

Abstract: 6G networks will bring forth a variety of novel enabling technologies such as
integrated sensing and communications for perceptive mobile networks,
quantum-enabled wireless networks, blockchainized mobile networks, and AI-native networks with intelligence-endogeneous capabilities. The push from more
advanced technological tools becoming available as well as the pull from
society’s needs imply that there must be several 6G paradigm shifts, e.g.,
transition from 2D to global 3D connectivity, services beyond communication,
and a cyber-physical continuum between the connected physical world of senses,
actions, and experiences and its programmable digital representations.
Importantly, NSF’s view on Next G research is that Next G includes but is not
limited to the specific key performance indicator requirements and topics of
interest addressed by the different 6G standards development organizations. In
fact, according to the Next G Alliance roadmap, there is a unique opportunity to
address the interdependencies between technological and human evolution,
given that there is a symbiotic relationship between technology and a
population’s societal and economic needs. As technology shapes human
behavior and lifestyles, those needs shape technological evolution.

This talk focuses on the fusion of digital and real worlds. We introduce the concept of the so-called Multiverse as an interesting attempt to help realize the fusion of digital and real worlds. The Multiverse offers eight different types of reality, including but not limited to virtual and augmented reality. A term closely related to the Multiverse is the recently emerging Metaverse. The Metaverse might be viewed as the next step after the
Internet, similar to how the mobile Internet expanded and enhanced the early Internet in the 1990s and 2000s. The various adventures that this place has to offer will surround us both socially and visually. The Metaverse will put the user first, allowing every member of our species to delve into new realms of possibilities. A modern, digital renaissance is taking place on the grandest stage we have ever seen, involving billions of connected
brains. In the coming decades, a new era of virtual life will bring in our next big milestone as a networked species.

Some argue that we are in the middle of making a historic pivot from adapting nature to our species to adapting our species back to nature. This pivot requires a wholesale rethinking of our worldview, shifting to a new scientific paradigm that views nature as a life source rather than resource and perceives the Earth as a complex self-organizing, and self-evolving system. While we know less about the ocean floor than we know about the surface of the moon, we know even less about the complex life that busies itself under our feet in the soil and cannot be seen with the naked eye. A handful of forest soil contains more life forms than there are people on the planet. The talk will end by providing an outlook on the convergence of digital evolution with biology, as
illustrated for the use case of Metaverse’s virtual society. We outline our ideas of the virtual society’s symbiosis of Inter(net) and (human) beings in the future Metaverse, giving rise to the powerful concept of Interbeing. We show that generative AI is instrumental in creating life-like digital organisms that produce clever solutions that AI researchers did not consider, had thought impossible, or even outwitting us humans

Biography: Martin Maier is a full professor with the Institut National de la Recherche Scientifique (INRS), Montréal, Canada. He was educated at the Technical University of Berlin, Germany, and received MSc and PhD degrees both with distinctions (summa cum laude) in 1998 and 2003, respectively. He was a recipient of the two-year Deutsche
Telekom doctoral scholarship from 1999 through 2001. He was a visiting researcher at the University of Southern California (USC), Los Angeles, CA, in 1998 and Arizona State University (ASU), Tempe, AZ, in 2001. In 2003, he was a postdoc fellow at the Massachusetts Institute of Technology (MIT), Cambridge, MA. Before joining INRS, Dr. Maier was a research associate at CTTC, Barcelona, Spain, 2003 through 2005. He was a
visiting professor at Stanford University, Stanford, CA, 2006 through 2007. He was a co-recipient of the 2009 IEEE Communications Society Best Tutorial Paper Award. Further, he was a Marie Curie IIF Fellow of the European Commission from 2014 through 2015. In 2017, he received the Friedrich Wilhelm Bessel Research Award from the Alexander von Humboldt (AvH) Foundation in recognition of his accomplishments in research
on FiWi-enhanced mobile networks. In 2017, he was named one of the three most promising scientists in the category “Contribution to a better society” of the Marie Skłodowska-Curie Actions (MSCA) 2017 Prize Award of the European Commission. In 2019/2020, he held a UC3M-Banco de Santander Excellence Chair at Universidad Carlos III de Madrid (UC3M), Madrid, Spain.

Solving Extreme-Scale Problems on Sunway Supercomputers

Speaker:  Prof. Haohuan Fu, Professor, Tsinghua University, Deputy Director, National Supercomputing Center

Date/Time: May 22nd (Monday) at 16:00 HKT

Abstract: defined as the fastest computers in the world by the name, supercomputers have been important tools for making scientific discoveries and technological breakthroughs. In this talk, we will introduce a series of Sunway Supercomputers, which demonstrate a  superb example of integrating tens of millions of cores into a specific scientific or engineering problem and bringing chances for widening our knowledge boundary. We would also provide examples on solving extreme-scale problems on Sunwaysupercomputers, in the domain of climate modeling, earthquake simulation, quantum simulation, understanding of satellite images. Through these examples, we discuss the key issues and important efforts required for bridging the computing power and the major challenges that we face.

Biography: Haohuan Fu is a Professor in the Department of Earth System Science, Tsinghua University, and the deputy director of the National Supercomputing Center in Wuxi. Fu has a Ph.D. in computing from Imperial College London. His research work focuses on supercomputing software, leading to three ACM Gordon Bell Prizes (non-hydrostatic atmospheric dynamic solver in 2016, nonlinear earthquake simulation in 2017, and random quantum circuit simulation in 2021).

ESSPER: Elastic and Scalable FPGA-Cluster System for High-Performance Reconfigurable Computing with Supercomputer Fugaku

Speaker:  Prof. Kentaro Sano, RIKEN Center for Computational Science, Japan

Date/Time: April 3rd (Monday) at 16:00 HKT

Abstract: At RIKEN Center for Computational Science (R-CCS), we have been developing an experimental FPGA Cluster named “ESSPER (Elastic and Scalable System for high-PErformance Reconfigurable computing),” which is a research platform for reconfigurable HPC. ESSPER is composed of sixteen Intel Stratix 10 SX FPGAs which are connected to each other by a dedicated 100Gbps inter-FPGA network. We have developed our own Shell (SoC) and its software APIs for the FPGAs supporting inter-FPGA communication. The FPGA host servers are connected to a 100Gbps Infiniband switch, which allows distant servers to remotely access the FPGAs by using a software bridged Intel’s OPAE FPGA driver, called R-OPAE. By 100Gbps Infiniband network and R-OPAE, ESSPER is actually connected to the world’s fastest supercomputer, Fugaku, deployed in RIKEN, so that using Fugaku we can program bitstreams onto FPGAs remotely using R-OPAE, and off-load tasks to the FPGAs. In this talk, I introduce our ESSPER’s concept, system stack of hardware and software, programming environment, under-development applications as well as our future prospects for reconfigurable HPC.

Biography: Dr. Kentaro Sano is the team leader of the processor research team at RIKEN Center for Computational Science (R-CCS) since 2017, responsible for research and development of future high-performance processors and systems. He is also a visiting professor with an advanced computing system laboratory at Tohoku University. He received his Ph.D. from the graduate school of information sciences, Tohoku University, in 2000. From 2000 until 2018, he was a Research Associate and an Associate Professor at Tohoku University. He was a visiting researcher at the Department of Computing, Imperial College, London, and Maxeler Technology corporation in 2006 and 2007. His research interests include data-driven and spatial-parallel processor architectures such as a coarse-grain reconfigurable array (CGRA), FPGA-based high-performance reconfigurable computing, high-level synthesis compilers and tools for reconfigurable custom computing machines, and system architectures for next-generation supercomputing based on the data-flow computing model.

A 40-minute Introduction to Post-Quantum Cryptography

Speaker:  Dr. David Jingwei Hu, Nanyang Technological University, Singapore

Date/Time: March 20th (Monday) at 16:00 HKT

Abstract: In this talk, I share my personal views on why post-quantum cryptography is important, then what post-quantum cryptography is, and finally, how we may conduct post-quantum cryptographic research. I will also share my study journey in Mainland, Hong Kong, and Singapore.

Biography: Jingwei Hu received his Ph.D. degree from the City University of Hong Kong in 2018. He is currently a postdoctoral research fellow at Nanyang Technological University, Singapore. He made contributions to several post-quantum cryptographic hardware designs, one side-channel analysis methodology for post-quantum cryptographic hardware, and one post-quantum algorithmic design. In 2022, the national institute of standards and technology released a status report on the Third Round of the NIST Post-Quantum Cryptography Standardization Process and stated that his work confirmed the performance of BIKE would be suitable for most applications. In 2021, he was nominated by Nanyang Technological University to participate in the 9th Global Young Scientists
Summit organized by National Research Foundation, Singapore. He won the Outstanding Academic Performance Award from the
City University of Hong Kong in 2017.

My Career Development as an Educator

Speaker:  Dr. Matthew Tang, Queen Mary University of London, UK

Date/Time: Feb 13th (Monday) at 16:00 HKT

Abstract: In this talk, I am going to look back at my career development in academia for the past 15 years. I will first share my experiences in various roles of an instructor, a lecturer, a center director, and an engineer, that I had been through in CUHK and QMUL. In particular, I would like to contrast the difference in the teaching environments between China, Hong Kong, and the United Kingdom. Furthermore, I will also highlight my thoughts on building the skill sets that enable effective lecture delivery and programme development. Lastly, I would like to discuss recent changes in higher education and invite the audience to a dialogue about the education of our future.

Biography: Matthew Wai-Chung Tang finished his B.Eng. in Computer Engineering, MPhil, and PhD in Computer Science and Engineering from the Chinese University of Hong Kong (CUHK) in 2003, 2005, and 2008 respectively. He is now a Senior Lecturer (Teaching and scholarship) in Computer Engineering at the School of Electric Engineering and Computer Science (EECS), Queen Mary University of London (QMUL). He teaches primarily in the QMUL-BUPT Joint Programme (JP). Currently, he is the Director of the JP Innovation Centre and the Programme Lead of the Internet of Things Engineering Programme. He received the Teaching Excellence Award from BUPT-QMUL Joint Programme in 2017/18. He is a Chartered Engineer, a fellow of the Higher Education Academy (HEA), and a member of IET and IEEE. Matthew is interested in RISC-V architecture and implementation, reconfigurable computing, and design automation algorithms for Field Programming Gate Arrays (FPGA). He receives the Celoxica Best Paper Award in the 2007 IEEE Southern Conference on Programmable Logic (SPL’07) and the Best Presentation Award in the 2007 International Ph.D. Workshop on SoC (IPS’07).

Security challenges and opportunities in emerging device technologies

Speaker:  Prof. Nele Mentens, Leiden University, The Netherlands & KU Leuven, Belgium

Date/Time: Jan 27th (Friday) at 16:00 HKT

Abstract: While traditional chips in bulk silicon technology are widely used for reliable and highly efficient systems, there are applications that call for devices in other technologies. On the one hand, novel device technologies need to be re-evaluated with respect to potential threats and attacks and how these can be faced with existing and novel security solutions and methods. On the other hand, emerging device technologies bring opportunities for building future security systems. This talk will give an overview of the minimal hardware resources that are needed to build secure systems and discusses the state-of-the-art in design of these hardware resources in emerging device technologies.

Biography: Nele Mentens is a professor at Leiden University in the Netherlands and KU Leuven in Belgium. Her research interests are in the field of configurable computing and hardware security. She was/is the PI in around 25 finished and ongoing research projects with national and international funding. She serves as a program committee member of renowned international security and hardware design conferences. She was the general co-chair of FPL’17, and she was/is the program chair of FPL’20, CARDIS’20, RAW’21, VLSID’22, DDECS’23, ASAP’23, and FPL’23. She is a (co-)author in around 150 publications in international journals, conferences, and books. She received best paper awards and nominations at CHES’19, AsianHOST’17, and DATE’16. Nele is an associate editor for IEEE TIFS, IEEE CAS Magazine, IEEE S&P, IEEE TCAD, ACM TRETS, and ACM TODAES. She also serves as an expert for the European Commission.

Edge Intelligence: Hardware Challenges and Opportunities

Speaker:  Prof. Jose Nunez-Yanez, Linköping University, Sweden

Date/Time: Dec 2th (Friday) at 16:00 HKT

Abstract: In this talk we will initially discuss some basic edge computing concepts followed by the hardware challenges and opportunities of performing deep learning at the edge. We will then present the FADES (Fused Architecture for DEnse and Sparse tensor processing) heterogeneous architecture focusing on its application to Graph neural networks (GNN) acceleration. GNNs can deliver high accuracy when applied to non-Euclidean data in which data elements do not fit into a regular structure. They combine sparse and dense data characteristics and this, in turn, results in a combination of compute and bandwidth intensive requirements challenging to meet with general purpose hardware. FADES is a highly configurable architecture fully described with high-level synthesis integrated in TensorFlow Lite and Pytorch. It creates a dataflow of dataflows with multiple hardware treads and compute units that optimize data access and processing element utilization. This enables fine-grained stream hybrid processing of sparse and dense tensors suitable for multi-layer graph neural networks.

Biography: Prof. Nunez-Yanez is a professor in hardware architectures for Machine Learning at Linköping University with over 20 years of experience in the design of high-performance embedded hardware. He holds a PhD in hardware-based parallel data compression from the University of Loughborough, UK, with three patents awarded on the topic of high-speed parallel data compression. Previously to joining Linköping University he was a reader (associate professor) at Bristol University, UK. He spent a few years working in industry at ST Micro (Milan), ARM (Cambridge) and Sensata Systems (Swindon) with Marie Curie and Royal Society fellowships. His main area of expertise is in the design of hardware architectures and heterogenous systems for signal processing and
machine learning with a focus on run-time adaptation, high-performance via parallelism and energy-efficiency.

FPGA Technology: from Chips to Tools to Systems

Speaker:  Prof. Dirk Koch, Heidelberg University

Date/Time: Nov 4th (Friday) at 16:00 HKT

Abstract: The Novel Computing Technologies (NCT) group at Heidelberg University works on mostly technology-focused aspects of reconfigurable computing. Our group maintains the open FABulous eFPGA framework which was used for the tape out of 10 chips so far. With that tool, we designed FPGA fabric clones of established Xilinx and Lattice FPGAs but also new fabrics that use memristor technology for configuration storage. Our GoAhead Partial reconfiguration tool allows the implementation of very adaptive FPGA systems where the FPGA resource utilization can be dynamically adjusted according to runtime requirements and operational conditions in a transparent manner, We use that to build a dynamic database processing system where accelerator modules are plugged together to processing pipelines for accelerating problems, that are only known at runtime. We also develop a security infrastructure that is required to operate FPGAs in data centers, and the talk will show how we crashed over 100 AWS F1 (FPGA) instances. More importantly, the talk will present the FPGADefender virus scanner that helps to prevent such attacks. Note that we vacant positions.

Biography: Dirk Koch is a Professor at the Heidelberg University. His main research interests are on run-time reconfigurable systems based 0n FPGAs. embedded systems, computer architecture, VLSI, and hardware security. Dirk developed techniques and tools for self-adaptive distributed embedded control systems based on FPGAs. Current research projects include database acceleration using FPGA-based stream processing, HPC, and exascale computing. as well as reconfigurable instruction set extensions for CPUs and using FPGAs in data centers. Dirk Koch is the author of the book Partial Reconfiguration on FPGAs’and a co-editor of the book “FPGAs for Software Programmers”

 

C.K.K.S. Bootstrapping

Speaker: Dr. Jingwei Hu

Date/Time: Oct 26th (Tuesday) at 10:00 AM Beijing Time (10:00 PM East Time)

Venue: Online Seminar (Zoom)

Language: English

 

Computing over encrypted data without bootstrapping

Speaker: Dr. Jingwei Hu

Date/Time: July 27th (Tuesday) at 9:00 PM Beijing Time (9:00 AM East Time)

Venue: Online Seminar (Zoom)

Language: English

 

Revisiting FHEW-like Homomorphic Encryptions

Speaker: Dr. Jingwei Hu

Date/Time: May 26th (Wednesday) at 10:30 AM Beijing Time (10:30 PM East Time)

Venue: Online Seminar (Zoom)

Language: English

 

Running Post-Quantum Cryptography on Real Hardware

Speaker: Dr. Wen Wang

Date/Time: March 31st (Wednesday) at 10:00 PM Beijing Time (10:00 AM East Time)

Venue: Online Seminar (Zoom)

Language: English

 

Coding Theory used in NIST Post-Quantum Cryptography Standardization (Part-II)

Speaker: Dr. Jingwei Hu

Date/Time: Oct 21st (Wednesday) at 9:00 PM Beijing Time (9:00 AM East Time)

Venue: Online Seminar (Zoom)

Language: English

 

Cryptos in Networks and Hardware Security

Speaker: Dr. Yao Liu

Date/Time: Oct 21st (Wednesday) at 9:00 PM Beijing Time (9:00 AM East Time)

Venue: Online Seminar (Zoom)

Language: English

 

Coding Theory used in NIST Post-Quantum Cryptography Standardization (Part-I)

Speaker: Dr. Jingwei Hu

Date/Time: Sept 9th (Wednesday) at 9:00 PM Beijing Time (9:00 AM East Time)

Venue: Online Seminar (Zoom)

Language: English

 

Sparse-Dense Polynomial Multiplication in Lightweight PQC

Speaker: Mr. Guangyan LI

Date/Time: Sept 9th (Wednesday) at 9:00 PM Beijing Time (9:00 AM East Time)

Venue: Online Seminar (Zoom)

Language: English

 

Implementation and Benchmarking of Round 2 Candidates in the NIST Post-Quantum Cryptography Standardization Process Using FPGAs

Speaker: Prof. Kris Gaj

Date/Time: Aug 19th (Tuesday) at 9:00 PM Beijing Time (9:00 AM East Time)

Venue: Online Seminar (Zoom)

Language: English

Slides: Link 

 

Recent Progress in Fully Homomorphic Encryptions (Part-II)

Speaker: Dr. Jingwei Hu

Date/Time: July 14th (Tuesday) at 9:00 PM Beijing Time (9:00 AM East Time)

Venue: Online Seminar (Zoom)

Language: English

 

Reviews on Number Theoretic Transform

Speaker: Dr. Donglong Chen

Date/Time: June 29th (Monday) at 9:00 PM Beijing Time (9:00 AM East Time)

Venue: Online Seminar (Zoom)

Language: English

 

Multiplication Algorithms in Lightweight PQC – Binary Ring-LWE

Speaker: Mr. Guangyan LI

Date/Time: June 23rd (Monday) at 8:00 PM Beijing Time (8:00 AM East Time)

Venue: Online Seminar (Zoom)

Language: English

 

Recent Progress in Fully Homomorphic Encryption (Part-I)

Speaker: Dr. Jingwei Hu

Date/Time: May 26th (Sunday) at 8:00 PM Beijing Time (8:00 AM East Time)

Venue: Online Seminar (Zoom)

Language: English

Comments are closed.