If you are interested in the upcoming or future seminars, please contact us for more information.
A 40-minute Introduction to Post-Quantum Cryptography
Speaker: Prof. Haohuan Fu, Professor, Tsinghua University, Deputy Director, National Supercomputing Center
Date/Time: May 22nd (Monday) at 16:00 HKT
Abstract: defined as the fastest computers in the world by the name, supercomputers have been important tools for making scientific discoveries and technological breakthroughs. In this talk, we will introduce a series of Sunway Supercomputers, which demonstrate a superb example of integrating tens of millions of cores into a specific scientific or engineering problem and bringing chances for widening our knowledge boundary. We would also provide examples on solving extreme-scale problems on Sunwaysupercomputers, in the domain of climate modeling, earthquake simulation, quantum simulation, understanding of satellite images. Through these examples, we discuss the key issues and important efforts required for bridging the computing power and the major challenges that we face.
Biography: Haohuan Fu is a Professor in the Department of Earth System Science, Tsinghua University, and the deputy director of the National Supercomputing Center in Wuxi. Fu has a Ph.D. in computing from Imperial College London. His research work focuses on supercomputing software, leading to three ACM Gordon Bell Prizes (non-hydrostatic atmospheric dynamic solver in 2016, nonlinear earthquake simulation in 2017, and random quantum circuit simulation in 2021).
A 40-minute Introduction to Post-Quantum Cryptography
Speaker: Prof. Kentaro Sano, RIKEN Center for Computational Science, Japan
Date/Time: April 3rd (Monday) at 16:00 HKT
Abstract: At RIKEN Center for Computational Science (R-CCS), we have been developing an experimental FPGA Cluster named “ESSPER (Elastic and Scalable System for high-PErformance Reconfigurable computing),” which is a research platform for reconfigurable HPC. ESSPER is composed of sixteen Intel Stratix 10 SX FPGAs which are connected to each other by a dedicated 100Gbps inter-FPGA network. We have developed our own Shell (SoC) and its software APIs for the FPGAs supporting inter-FPGA communication. The FPGA host servers are connected to a 100Gbps Infiniband switch, which allows distant servers to remotely access the FPGAs by using a software bridged Intel’s OPAE FPGA driver, called R-OPAE. By 100Gbps Infiniband network and R-OPAE, ESSPER is actually connected to the world’s fastest supercomputer, Fugaku, deployed in RIKEN, so that using Fugaku we can program bitstreams onto FPGAs remotely using R-OPAE, and off-load tasks to the FPGAs. In this talk, I introduce our ESSPER’s concept, system stack of hardware and software, programming environment, under-development applications as well as our future prospects for reconfigurable HPC.
Biography: Dr. Kentaro Sano is the team leader of the processor research team at RIKEN Center for Computational Science (R-CCS) since 2017, responsible for research and development of future high-performance processors and systems. He is also a visiting professor with an advanced computing system laboratory at Tohoku University. He received his Ph.D. from the graduate school of information sciences, Tohoku University, in 2000. From 2000 until 2018, he was a Research Associate and an Associate Professor at Tohoku University. He was a visiting researcher at the Department of Computing, Imperial College, London, and Maxeler Technology corporation in 2006 and 2007. His research interests include data-driven and spatial-parallel processor architectures such as a coarse-grain reconfigurable array (CGRA), FPGA-based high-performance reconfigurable computing, high-level synthesis compilers and tools for reconfigurable custom computing machines, and system architectures for next-generation supercomputing based on the data-flow computing model.
A 40-minute Introduction to Post-Quantum Cryptography
Speaker: Dr. David Jingwei Hu, Nanyang Technological University, Singapore
Date/Time: March 20th (Monday) at 16:00 HKT
Abstract: In this talk, I share my personal views on why post-quantum cryptography is important, then what post-quantum cryptography is, and finally, how we may conduct post-quantum cryptographic research. I will also share my study journey in Mainland, Hong Kong, and Singapore.
Biography: Jingwei Hu received his Ph.D. degree from the City University of Hong Kong in 2018. He is currently a postdoctoral research fellow at Nanyang Technological University, Singapore. He made contributions to several post-quantum cryptographic hardware designs, one side-channel analysis methodology for post-quantum cryptographic hardware, and one post-quantum algorithmic design. In 2022, the national institute of standards and technology released a status report on the Third Round of the NIST Post-Quantum Cryptography Standardization Process and stated that his work confirmed the performance of BIKE would be suitable for most applications. In 2021, he was nominated by Nanyang Technological University to participate in the 9th Global Young Scientists
Summit organized by National Research Foundation, Singapore. He won the Outstanding Academic Performance Award from the
City University of Hong Kong in 2017.
My Career Development as an Educator
Speaker: Dr. Matthew Tang, Queen Mary University of London, UK
Date/Time: Feb 13th (Monday) at 16:00 HKT
Abstract: In this talk, I am going to look back at my career development in academia for the past 15 years. I will first share my experiences in various roles of an instructor, a lecturer, a center director, and an engineer, that I had been through in CUHK and QMUL. In particular, I would like to contrast the difference in the teaching environments between China, Hong Kong, and the United Kingdom. Furthermore, I will also highlight my thoughts on building the skill sets that enable effective lecture delivery and programme development. Lastly, I would like to discuss recent changes in higher education and invite the audience to a dialogue about the education of our future.
Biography: Matthew Wai-Chung Tang finished his B.Eng. in Computer Engineering, MPhil, and PhD in Computer Science and Engineering from the Chinese University of Hong Kong (CUHK) in 2003, 2005, and 2008 respectively. He is now a Senior Lecturer (Teaching and scholarship) in Computer Engineering at the School of Electric Engineering and Computer Science (EECS), Queen Mary University of London (QMUL). He teaches primarily in the QMUL-BUPT Joint Programme (JP). Currently, he is the Director of the JP Innovation Centre and the Programme Lead of the Internet of Things Engineering Programme. He received the Teaching Excellence Award from BUPT-QMUL Joint Programme in 2017/18. He is a Chartered Engineer, a fellow of the Higher Education Academy (HEA), and a member of IET and IEEE. Matthew is interested in RISC-V architecture and implementation, reconfigurable computing, and design automation algorithms for Field Programming Gate Arrays (FPGA). He receives the Celoxica Best Paper Award in the 2007 IEEE Southern Conference on Programmable Logic (SPL’07) and the Best Presentation Award in the 2007 International Ph.D. Workshop on SoC (IPS’07).
Security challenges and opportunities in emerging device technologies
Speaker: Prof. Nele Mentens, Leiden University, The Netherlands & KU Leuven, Belgium
Date/Time: Jan 27th (Friday) at 16:00 HKT
Abstract: While traditional chips in bulk silicon technology are widely used for reliable and highly efficient systems, there are applications that call for devices in other technologies. On the one hand, novel device technologies need to be re-evaluated with respect to potential threats and attacks and how these can be faced with existing and novel security solutions and methods. On the other hand, emerging device technologies bring opportunities for building future security systems. This talk will give an overview of the minimal hardware resources that are needed to build secure systems and discusses the state-of-the-art in design of these hardware resources in emerging device technologies.
Biography: Nele Mentens is a professor at Leiden University in the Netherlands and KU Leuven in Belgium. Her research interests are in the field of configurable computing and hardware security. She was/is the PI in around 25 finished and ongoing research projects with national and international funding. She serves as a program committee member of renowned international security and hardware design conferences. She was the general co-chair of FPL’17, and she was/is the program chair of FPL’20, CARDIS’20, RAW’21, VLSID’22, DDECS’23, ASAP’23, and FPL’23. She is a (co-)author in around 150 publications in international journals, conferences, and books. She received best paper awards and nominations at CHES’19, AsianHOST’17, and DATE’16. Nele is an associate editor for IEEE TIFS, IEEE CAS Magazine, IEEE S&P, IEEE TCAD, ACM TRETS, and ACM TODAES. She also serves as an expert for the European Commission.
Edge Intelligence: Hardware Challenges and Opportunities
Speaker: Prof. Jose Nunez-Yanez, Linköping University, Sweden
Date/Time: Dec 2th (Friday) at 16:00 HKT
Abstract: In this talk we will initially discuss some basic edge computing concepts followed by the hardware challenges and opportunities of performing deep learning at the edge. We will then present the FADES (Fused Architecture for DEnse and Sparse tensor processing) heterogeneous architecture focusing on its application to Graph neural networks (GNN) acceleration. GNNs can deliver high accuracy when applied to non-Euclidean data in which data elements do not fit into a regular structure. They combine sparse and dense data characteristics and this, in turn, results in a combination of compute and bandwidth intensive requirements challenging to meet with general purpose hardware. FADES is a highly configurable architecture fully described with high-level synthesis integrated in TensorFlow Lite and Pytorch. It creates a dataflow of dataflows with multiple hardware treads and compute units that optimize data access and processing element utilization. This enables fine-grained stream hybrid processing of sparse and dense tensors suitable for multi-layer graph neural networks.
Biography: Prof. Nunez-Yanez is a professor in hardware architectures for Machine Learning at Linköping University with over 20 years of experience in the design of high-performance embedded hardware. He holds a PhD in hardware-based parallel data compression from the University of Loughborough, UK, with three patents awarded on the topic of high-speed parallel data compression. Previously to joining Linköping University he was a reader (associate professor) at Bristol University, UK. He spent a few years working in industry at ST Micro (Milan), ARM (Cambridge) and Sensata Systems (Swindon) with Marie Curie and Royal Society fellowships. His main area of expertise is in the design of hardware architectures and heterogenous systems for signal processing and
machine learning with a focus on run-time adaptation, high-performance via parallelism and energy-efficiency.
FPGA Technology: from Chips to Tools to Systems
Speaker: Prof. Dirk Koch, Heidelberg University
Date/Time: Nov 4th (Friday) at 16:00 HKT
Abstract: The Novel Computing Technologies (NCT) group at Heidelberg University works on mostly technology-focused aspects of reconfigurable computing. Our group maintains the open FABulous eFPGA framework which was used for the tape out of 10 chips so far. With that tool, we designed FPGA fabric clones of established Xilinx and Lattice FPGAs but also new fabrics that use memristor technology for configuration storage. Our GoAhead Partial reconfiguration tool allows the implementation of very adaptive FPGA systems where the FPGA resource utilization can be dynamically adjusted according to runtime requirements and operational conditions in a transparent manner, We use that to build a dynamic database processing system where accelerator modules are plugged together to processing pipelines for accelerating problems, that are only known at runtime. We also develop a security infrastructure that is required to operate FPGAs in data centers, and the talk will show how we crashed over 100 AWS F1 (FPGA) instances. More importantly, the talk will present the FPGADefender virus scanner that helps to prevent such attacks. Note that we vacant positions.
Biography: Dirk Koch is a Professor at the Heidelberg University. His main research interests are on run-time reconfigurable systems based 0n FPGAs. embedded systems, computer architecture, VLSI, and hardware security. Dirk developed techniques and tools for self-adaptive distributed embedded control systems based on FPGAs. Current research projects include database acceleration using FPGA-based stream processing, HPC, and exascale computing. as well as reconfigurable instruction set extensions for CPUs and using FPGAs in data centers. Dirk Koch is the author of the book Partial Reconfiguration on FPGAs’and a co-editor of the book “FPGAs for Software Programmers”
C.K.K.S. Bootstrapping
Speaker: Dr. Jingwei Hu
Date/Time: Oct 26th (Tuesday) at 10:00 AM Beijing Time (10:00 PM East Time)
Venue: Online Seminar (Zoom)
Language: English
Computing over encrypted data without bootstrapping
Speaker: Dr. Jingwei Hu
Date/Time: July 27th (Tuesday) at 9:00 PM Beijing Time (9:00 AM East Time)
Venue: Online Seminar (Zoom)
Language: English
Revisiting FHEW-like Homomorphic Encryptions
Speaker: Dr. Jingwei Hu
Date/Time: May 26th (Wednesday) at 10:30 AM Beijing Time (10:30 PM East Time)
Venue: Online Seminar (Zoom)
Language: English
Running Post-Quantum Cryptography on Real Hardware
Speaker: Dr. Wen Wang
Date/Time: March 31st (Wednesday) at 10:00 PM Beijing Time (10:00 AM East Time)
Venue: Online Seminar (Zoom)
Language: English
Coding Theory used in NIST Post-Quantum Cryptography Standardization (Part-II)
Speaker: Dr. Jingwei Hu
Date/Time: Oct 21st (Wednesday) at 9:00 PM Beijing Time (9:00 AM East Time)
Venue: Online Seminar (Zoom)
Language: English
Cryptos in Networks and Hardware Security
Speaker: Dr. Yao Liu
Date/Time: Oct 21st (Wednesday) at 9:00 PM Beijing Time (9:00 AM East Time)
Venue: Online Seminar (Zoom)
Language: English
Coding Theory used in NIST Post-Quantum Cryptography Standardization (Part-I)
Speaker: Dr. Jingwei Hu
Date/Time: Sept 9th (Wednesday) at 9:00 PM Beijing Time (9:00 AM East Time)
Venue: Online Seminar (Zoom)
Language: English
Sparse-Dense Polynomial Multiplication in Lightweight PQC
Speaker: Mr. Guangyan LI
Date/Time: Sept 9th (Wednesday) at 9:00 PM Beijing Time (9:00 AM East Time)
Venue: Online Seminar (Zoom)
Language: English
Implementation and Benchmarking of Round 2 Candidates in the NIST Post-Quantum Cryptography Standardization Process Using FPGAs
Speaker: Prof. Kris Gaj
Date/Time: Aug 19th (Tuesday) at 9:00 PM Beijing Time (9:00 AM East Time)
Venue: Online Seminar (Zoom)
Language: English
Slides: Link
Recent Progress in Fully Homomorphic Encryptions (Part-II)
Speaker: Dr. Jingwei Hu
Date/Time: July 14th (Tuesday) at 9:00 PM Beijing Time (9:00 AM East Time)
Venue: Online Seminar (Zoom)
Language: English
Reviews on Number Theoretic Transform
Speaker: Dr. Donglong Chen
Date/Time: June 29th (Monday) at 9:00 PM Beijing Time (9:00 AM East Time)
Venue: Online Seminar (Zoom)
Language: English
Multiplication Algorithms in Lightweight PQC – Binary Ring-LWE
Speaker: Mr. Guangyan LI
Date/Time: June 23rd (Monday) at 8:00 PM Beijing Time (8:00 AM East Time)
Venue: Online Seminar (Zoom)
Language: English
Recent Progress in Fully Homomorphic Encryption (Part-I)
Speaker: Dr. Jingwei Hu
Date/Time: May 26th (Sunday) at 8:00 PM Beijing Time (8:00 AM East Time)
Venue: Online Seminar (Zoom)
Language: English