For the latest publication list, you can access CityU Scholar page here:
Muhammad Irfan, Zahid Ullah, and Ray C.C. Cheung. “A High performance Distributed RAM based TCAM Architecture on FPGAs” IEEE Access(accepted).
Biao Min, Wei-pei Huang, Ray C.C. Cheung, Hong Yan. “A High Performance Hardware Architecture for Non-negative Tensor Factorization”. Microelectronics Journal. |PDF
Hulin Kuang, Long Chen, Leanne Lai Hang Chan, Ray C. C. Cheung, and Hong Yan. “Feature Selection Based on Tensor Decomposition and Object Proposal for Nighttime Multi-class Vehicle Detection”. IEEE Transactions on Systems, Man, and Cybernetics: Systems. |PDF
Wei-pei Huang, Bowen P.Y. Kwan, Weiyang Ding, Biao Min, Ray C.C. Cheung, Liqun Qi, Hong Yan “High performance hardware architecture for singular spectrum analysis of Hankel tensors”. Microprocessors and Microsystems.|PDF
Zhe Xu, Biao Min, Ray C.C. Cheung. “A robust background initialization algorithm with superpixel motion detection”. Signal Processing: Image Communication. Volume 71, pp. 1-12. |PDF
Zhe Xu, Biao Min, Ray C.C. Cheung. “A fast inter CU decision algorithm for HEVC”. Signal Processing: Image Communication. Volume 60, pp. 211-223. |PDF
Jingwei Hu, and Ray C. C. Cheung. “Toward Practical Code-Based Signature: Implementing Fast and Compact QC-LDGM Signature Scheme on Embedded Hardware”. IEEE Transactions on Circuits and Systems I: Regular Papers, Volume 64, Issue: 8, PP 2086-2097, Aug, 2017 | PDF
Jingwei Hu, Ray C. C. Cheung, and Tim Guneysu. “Compact Constant Weight Coding Engines for the Code-Based Cryptography”. IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 64, Issue: 9, PP 1092-1096, Sep, 2017 | PDF
Jingwei Hu, and Ray C. C. Cheung. “Area-Time Efficient Computation of Niederreiter Encryption on QC-MDPC Codes for Embedded Hardware”. IEEE Transactions on Computers, Volume 66, Issue: 8, PP 1313-1325, Aug, 2017 | PDF
Yao Liu, Xiao-Zhou Li, Ray C.C. Cheung, Sze-Chun Chan, Hei Wong, “High-speed Discrete Gaussian Sampler with Heterodyne Chaotic Laser Inputs,” IEEE Transactions on Circuits and Systems II: Express Briefs. |PDF
Qian Zhou, Yan Han, Shifeng Zhang, Xiaoxia Han, Ray C. C. Cheung & Guangtao Feng, “A V-band VCO with on-chip body bias voltage control technique using 40-nm CMOS process,” Journal of Electromagnetic Waves and Applications, Volume 31, Issue:5, PP 514-521, Mar. 2017 | PDF
Wangchen Dai, Donald Donglong Chen, Ray C.C. Cheung, Cetin Kaya Koc, “Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication,” IEEE Transactions on Computers, Volume: 66, Issue: 3, PP 375-388, Mar. 2017. | PDF
Yao Liu, Ray C.C. Cheung, Hei Wong, “A Bias-bounded Digital True Random Number Generator Architecture,” IEEE Transactions on Circuits and Systems I: Regular Papers, Volume: 64, Issue: 1, PP 133-144, Jan. 2017. | PDF
Biao Min, Zhe Xu, and Ray C.C. Cheung, “A Fully Pipelined Hardware Architecture for Intra Prediction of HEVC,” IEEE Transactions on Circuits and Systems for Video Technology, accepted for publication as a Transactions Paper, June 2016. | PDF
W.X.Y. Li, R. Cheung, et al., “An FPGA based High-performance Neural Ensemble Spiking Activity Simulator Utilizing Generalized Volterra Kernel and Complexity Analysis”, Journal of Circuits, Systems and Computers, Volume 25, Issue 01, Jan. 2016. | PDF
D. D. Chen, G. X. Yao, R. C. C. Cheung, D. Pao, and Ç. K. Koç. “Parameter space for the architecture of FFT-based Montgomery modular multiplication”. IEEE Transactions on Computers, Volume: 65, Issue: 1, PP 147-160, Jan. 2016. | PDF
Jingwei Hu, Wei Guo, Jizeng Wei, and Ray C. C. Cheung. “Fast Inversion Architectures over GF(2m) Using Modified Itoh-Tsujii Algorithms”. IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 62, Issue: 4, PP 367-371, Apr, 2015 | PDF
Y. Xin, W.X.Y. Li, Z. Zhang, R.C.C. Cheung, D. Song, T.W. Berger, “An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics”, IEEE/ACM Transactions on Computational Biology and Bioinformatics, Volume 12, Issue 5, PP 1034-1047, Sep. 2015. | PDF
M. Jaiswal, B. Verma, H. So, M. Balakrishnan, K. Paul, Ray C.C. Cheung, “Configurable Architectures for Multi-Mode Floating Point Adders”, IEEE Transactions on Circuits and System I: Regular Papers, Volume: 62, Issue: 8, PP 2079-2090, Aug. 2015. | PDF
Biao Min, and Ray C.C. Cheung, “A Fast CU Size Decision Algorithm for HEVC Intra Encoder,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 25, no. 5, pp. 892-896, May 2015. | PDF
D. D. Chen, N. Mentens, F. Vercauteren, S. S. Roy, R. C.C. Cheung, D. Pao, and I. Verbauwhede, “High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.62, no.1, pp.157-166, Jan. 2015. | PDF
Y. Xin, W.X.Y. Li, R.C.C. Cheung, R.H.M. Chan, H. Yan, Dong Song, Theodore W. Berger, “An FPGA based Scalable Architecture of a Stochastic State Point Process Filter (SSPPF) to Track the Nonlinear Dynamics Underlying Neural Spiking”, Microelectronics Journal, 45(6): 690-701, 2014. | PDF
B.B. Liu, C.W. Yu, D.Z. Wang, R.C.C. Cheung, H. Yan, “Design Exploration of Geometric Biclustering for Microarray Data Analysis in Data Mining”, IEEE Transactions on Parallel and Distributed Systems, Vol. 25, Issue 10, pp. 2540–2550, Oct. 2014. | PDF
B.B. Liu, Y. Xin; R.C.C. Cheung, H. Yan, “GPU-based Biclustering for Microarray Data Analysis in Neurocomputing”, Neurocomputing Journal, Elsevier, Jun. 2014. | PDF
H. Luo, Y. Han, R.C.C. Cheung, X. Liu, and T. Cao, “A 0.8-V 230-uW 98-dB DR Inverter-Based Sigma-Delta Modulator for Audio Applications”, IEEE Journal of Solid-State Circuits, Vol 48(10), pp. 2430-2441, Oct. 2013. | PDF
Y. Han, X.P. Liu, X.X. Han, H. Luo, Ray C.C. Cheung, T.L. Cao, “A low-power inverter-based Sigma-Delta ADC for audio applications”, SCIENCE CHINA Information Sciences, 2013.
G. Yao, R.C.C. Cheung, J.F. Fan, I. Verbauwhede “Novel RNS Parameter Selection for Fast Modular Multiplication”, IEEE Transactions on Computers, 2013. | PDF
X. Yao, B.B. Liu, B. Min; W.X.Y. Li, R.C.C. Cheung, A.S. Fong, T.F. Chan, “Parallel Architecture for DNA Sequence Inexact Match with Burrows-Wheeler Transform”, Microelectronics Journal, Elsevier, 44(8):670-682, 2013. | PDF
W.X.Y. Li, R.C.C. Cheung, R.H.M. Chan, D. Song, T.W. Berger, “Real-Time Prediction of Neuronal Population Spiking Activity Using FPGA”, IEEE Transactions on Biomedical Circuits and Systems, Vol. PP, Issue 99, pp. 1-10, 2013 | PDF.
M. Jaiswal, and R.C.C. Cheung, “Area-Efficient Architectures for Double Precision Multiplier on FPGA, with Run-time-Reconfigurable Dual Single Precision Support”, Microelectronics Journal, Springer, Vol. 44, Issue 5, pp 421-430, 2013. | PDF
D. Pao, N.L. Or, R.C.C. Cheung, “A Memory-Based NFA Regular Expression Match Engine for Signature-Based Intrusion Detection Computer Communications”, Computer Communications, Elsevier, In Press, 2013. | PDF
B. Min, R.C.C. Cheung, and H. Yan, “A Flexible and Customizable Architecture for Relaxation Labeling Algorithm”, IEEE Transactions on Circuits and Systems II, 2013. PDF
H. Luo, Y. Han, R.C.C. Cheung, G. Liang, D. Zhu, “Subthreshold CMOS voltage reference circuit with body bias compensation for process variation”, IET Circuits, Devices & Systems, Vol. 6(3), 198-203, 2012. PDF.
M. Jaiswal, and R.C.C. Cheung, “VLSI Implementation of Double Precision Floating-Point Multiplier using Karatsuba Technique”, Circuits, Systems & Signal Processing (CSSP), Springer, Feb 2013, Vol. 32, Issue 1, pp 15-27. | PDF
H. Fan, Y.L. Wu, and R.C.C. Cheung, “Design Automation Framework for Reconfigurable Interconnection Networks”, The Computer Journal 2012; doi: 10.1093/comjnl/bxs136. | PDF.
J. Sum, C. Leung, R.C.C. Cheung, and T. Ho, “HEALPIX DCT technique for compressing PCA-based illumination adjustable images”, Neural computing & Applications, 21, 2012 | PDF.
Z. Wang, C.W. Yu, R.C.C. Cheung, H. Yan, “Hypergraph based Geometric Biclustering Algorithm”, Pattern Recognition Letters, Available online 22 May 2012, ISSN 0167-8655, 10.1016/j.patrec.2012.05.001. PDF.
Will X.Y. Li, Rosa H.M. Chan, Wei Zhang, R.C.C. Cheung, Dong Song, Theodore W. Berger, “High-performance and Scalable System Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking Activities”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), pp. 489-501, 2011. | PDF
M. Jaiswal, and R.C.C. Cheung, “High Performance FPGA Implementation of Double Precision Floating Point Adder/Subtractor”, International Journal of Hybrid Information Technology, SERSC, Oct, 2011 | PDF
Z. Hao, H. Xiaowei, H. Yan, R.C.C. Cheung, H. Xiaoxia, W. Hao, and L. Guo, “An 18-bit high performance audio sigma-delta D/A converter”, in Journal of Semiconductors, 31(7), 2010 | PDF
Hao Luo, Yan Han, R.C.C. Cheung, Xiaoxia Han, and Dazhong Zhu, “Bulk-compensated technique and its application to sub-threshold ICs”, in Electronic Letters, 46(16), pp. 1105-1106, 2010. | PDF
Luo Hao, Han Yan, Ray C. C. Cheung, Han Xiaoxia, Ma Shaoyu, Ying Peng and Zhu Dazhong, “A high-performance, low-power Sigma-Delta ADC for digital audio applications”, in Journal of Semiconductors, Volume 31, Issue 5, 2010. | PDF
D. Lee, R.C.C. Cheung, W. Luk, and J.D. Villasenor, “Hierarchical Segmentation for Hardware Function Evaluation”, in IEEE Transactions on VLSI Systems, 17(1), Jan, 2009. | PDF
D. Lee, R.C.C. Cheung, W. Luk, and J.D. Villasenor, “Hardware Implementation tradeoffs of Polynomial approximations and Interpolations”, in IEEE Transactions on Computers, Vol.57(5), pp.686-701, May,2008. | PDF
R.C.C. Cheung, D. Lee, W. Luk, and J.D. Villasenor, “Hardware Generation of Arbitrary Random Number Distributions from Uniform Distributions via the Inversion Method”, in IEEE Transactions on Very Large Scale Integration Systems, Vol. 15(8), 952-962, August, 2007. | PDF
D. Lee, R.C.C. Cheung, and J.D. Villasenor, “A Flexible Architecture for Precise Gamma Correction “, in IEEE Transactions on Very Large Scale Integration Systems, Vol. 15(4), 474-478, April, 2007. | PDF
H. Fan, J. Liu, Y.L. Wu, and C.C. Cheung, “The Exact Channel Density Bound and Compound Design for Generic Universal Switch Blocks,” in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 12(2), April, 2007. | PDF
D. Lee, A. Abdul Gaffar, R.C.C. Cheung, O. Mencer, W. Luk, and G.A. Constantinides, “Accuracy Guaranteed Bit-Width Optimization”, in IEEE Transactions on Computer-Aided Design, Vol. 25(10), 1990-2000, October, 2006. | PDF
H. Fan, Y.L. Wu, C.C. Cheung and J. Liu, “Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes,” in IEEE Transactions on Computers, Vol. 55(4), pp. 373-384, April, 2006. | PDF
R.C.C. Cheung, N. Telle, W. Luk, and P.Y.K. Cheung, “Customisable Elliptic Curve Cryptosystems”, in IEEE Transactions on Very Large Scale Integration Systems, Vol. 13(9), pp. 1048-1059, September, 2005. | PDF
H. Fan, J. Liu, Y.L. Wu, and C.C. Cheung, “On Optimal Hyper-universal and Rearrangeable Switch Box Designs,” in IEEE Transactions on Computer-Aided Design, Vol. 22(12), pp. 1637-1649, December, 2003. | PDF
Y.L. Wu, C.C. Cheung, D.I. Cheng, and H.B. Fan, “Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques,” in IEEE Transactions on Very Large Scale Integration Systems, Vol. 11(3), pp. 451-460, June, 2003. | PDF