Muhammad Irfan, R.C.C. Cheung, “High-Throughput Re-configurable content addressable memory on FPGAs”, ITCC2019, Singapore, 2019.
Abdurrashid Ibrahim Sanka, R.C.C. Cheung,”Efficient High Performance FPGA Based NoSQL Caching System For Blockchain Scalability and Throughput Improvement”, ICSEng 2018, Sydney, 2018.
Zhenya Zang, Yao Liu, R.C.C. Cheung,”Reconfigurable RISC-V Secure Processor And SoC Integration”, ICIT2019, Melburne, 2019.
Z. Ullah, R. Cheung, et al., “UE-TCAM: An Ultra Efficient SRAM-Based TCAM”, IEEE TENCON, Macau and Hong Kong, 2015.
Biomedical and Bioinformatic Circuit Designs
W.X.Y. Li, R.C.C. Cheung, R.H.M. Chan, D. Song, and T.W. Berger, “A Reconfigurable Architecture for Real-Time Prediction of Neural Activity”, to appear, ISCAS’13, Beijing, 2013.| PDF
C. Wang, X. Li, X. Zhou, J. Martin and R.C.C. Cheung, “Genome Sequencing Using MapReduce on FPGA with Multiple Hardware Accelerators”, to appear, FPGA, 2013.
A.W.Y. Lo, B. Liu, and R.C.C. Cheung, “GPU-Based Biclustering for Neural Information Processing”, the 19th International Conference on Neural Information Processing (ICONIP2012), Qatar, Nov, 2012.
W. Li, R.H.M. Chan, W. Zhang, R.C.C. Cheung, D. Song, and T.W. Berger, ” FPGA-Based Prototyping of Generalized Laguerre-Volterra MIMO Model for Neural Science Research”, International conference on Field-Programmable Logic and Applications (FPL), Greece, Sept, 2011.
W. Li, R.C.C. Cheung, W. Zhang, R.H.M. Chan, D. Song, and T.W. Berger, “FPGA architecture of generalized laguerre-volterra MIMO model for neural population spiking activities”, International symposium on Field-Programmable Custom Computing Machines, FCCM, 2011.
P. Zhu, R.C.C. Cheung, H. Li, L. Cui, and B. Hu, “FPGA-based Acceleration for Graph Similarity”, Design, Automation and Test in Europe, March, 2011.
C.W. Yu, Z. Wang, R.C.C. Cheung, and H. Yan, “An FPGA-based Geometric Biclustering Accelerator for Genes microarray Data Analysis”, Design, Automation and Test in Europe, March, 2011.
Cryptographic hardware designs
B. Min, R.C.C. Cheung, and Y. Han, “FPGA-based High-Throughput and Area-Efficient Architectures of the Hummingbird Cryptography”, the 37th Annual Conference of the IEEE Industrial Electronics Society (IECON), Melbourne, Australia, Nov, 2011.
R.C.C. Cheung, S. Duquesne, J. Fan, N. Guillermin, I. Verbauwhede, G.X. Yao, “FPGA Implementations of Pairing using Residue Number System and Lazy Reduction”, International Workshop on Cryptographic Hardware and Embedded Systems(CHES), Nara, Japan, Oct, 2011.
J. Szefer, W. Zhang, Y.Y. Chen, D. Champagne, K. Chan, X.Y. Li, R.C.C. Cheung, and R. Lee, “Rapid Single-Chip Secure Processor Prototyping on OpenSPARC FPGA Platform”, IEEE International Symposium on Rapid System Prototyping (RSP), Germany, 24-27 May 2011.
X. Yao, R.C.C. Cheung, C.K. Koc, and K.F. Man, “Reconfigurable number theoretic transform architectures for cryptographic applications”, 2010 International Conference on Field-Programmable Technology, FPT’10, Beijing, PRC, 8-10 December 2010, pp 308-311.
X. Yao, R.C.C. Cheung, and K.F. Man, “Counter Embedded Memory Architecture for Trusted Computing Platform”, to appear in Proceedings of the IEEE Symposium on Rapid System Prototyping (RSP), Virginia, USA, 2010.
R.C.C. Cheung, C.K. Koc, and J.D. Villasenor, “A High-Performance Hardware Architecture for Spectral Hash Algorithm”, to appear in Proceedings of IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Boston, MA, USA, 2009.
R.C.C. Cheung, W. Luk, and P.Y.K. Cheung, “Reconfigurable Elliptic Curve Cryptosystem on a Chip”, in Proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 24-29, Vol. 1, March, Munich, Germany, 2005. | PDF
R.C.C. Cheung, A. Brown, W. Luk, and P.Y.K. Cheung, “A Scalable Hardware Architecture for Prime Number Validation”, in Proceedings of IEEE International Conference on Field Programmable Technology (FPT), pp. 177-184, Dec, Brisbane, Australia, 2004. | PDF
N. Telle, W. Luk and R.C.C. Cheung, “Customising Hardware Designs for Elliptic Curve Cryptography”, in Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS’04), pp. 274-283, Samos, Greece, 2004.
Computer Arithmetic
M.K. Jaiswal, and R.C.C. Cheung, “Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier”, to appear in IEEE International Conference on Reconfigurable Architectures Workshop (RAW 2012), Shanghai, China, May, 2012. |
Z. Ullah, M.K. Jaiswal, Y.C. Chan, and R.C.C. Cheung, “FPGA Implementation of SRAM-basedTernary Content Addressable Memory”, to appear in IEEE International Conference on Reconfigurable Architectures Workshop (RAW 2012), Shanghai, China, May, 2012. |
M.K. Jaiswal, and R.C.C. Cheung, “High Performance Reconfigurable Architecture for Double Precision Floating Point Division”, to appear in International Symposium on Applied Reconfigurable Computing (ARC 2012), Hong Kong, China, March, 2012. |
W. Osborne, J. Coutinho, R.C.C. Cheung, W. Luk, and O. Mencer, “Instrumented Multi-stage Word-length Optimization”, to appear in IEEE International Conference on Field-Programmable Technology, Japan, Dec, 2007. | PDF
W. Osborne, R.C.C. Cheung, J. Coutinho, and W. Luk, “Automatic Accuracy Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems”, to appear in IEEE International Conference on Field-Programmable Logic and Applications (FPL), Netherlands, Aug, 2007. | PDF
D. Lee, R.C.C. Cheung, J.D. Villasenor, and W. Luk, “Inversion-based hardware Gaussian random number generator: a case study of function evaluation via hierarchical segmentation”, in IEEE International Conference on Field-Programmable Technology (FPT), pp. 33-40, Bangkok, Thailand, Dec, 2006. | PDF | Slides
R.C.C. Cheung, D. Lee, O. Mencer, W. Luk, and P.Y.K. Cheung, “Automating Custom-Precision Function Evaluation for Embedded Processors”, in ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 22-31, San Francisco, Sept, 2005. | PDF | Slides
G.L. Zhang, P.H.W. Leong, D. Lee, J.D. Villasenor, R.C.C. Cheung and W. Luk, Hardware architecture for a Ziggurat-based Gaussian random number generator, in IEEE International Conference on Field Programmable Logic and its Applications (FPL), pp. 275-280, Finland, Aug, 2005. |PDF
G.L. Zhang, P.H.W. Leong, C.H. Ho, K.H. Tsoi, C.C.C. Cheung, D. Lee, R.C.C. Cheung and W. Luk, “Reconfigurable Acceleration for Monte Carlo based Financial Simulation”, in IEEE International Conference on Field-Programmable Technology (FPT), pp. 215-222, Singapore, Dec, 2005. | PDF | Slides
Digital Circuit Designs
P. Zhu, C. Zhang, H. Li, R.C.C. Cheung, B. Hu, “An FPGA-Based Acceleration Platform for Auction Algorithm “, in Proceedings of the IEEE International Symposium on Circuits & Systems ISCAS’12, Seoul, Korea, May, 2012. | PDF
R.C.C. Cheung, K.P. Pun, Steve C.L. Yuen, K.H. Tsoi and Philip H.W. Leong, “An FPGA-based Re-configurable 24-bit 96kHz Sigma-Delta Audio DAC”, in Proceedings of the IEEE International Conference on Field Programmable Technology (FPT), pp. 110-117, Tokyo, Japan, Dec, 2003. |PDF
P.K. Tsang, C.C. Cheung, K.H. Leung, T.K. Lee and and P.H.W. Leong, “An Asynchronous Forth Microprocessor”, Proceedings of the IEEE Region 10 Conference (TENCON), Vol. 2, pp. 1079-1082, Korea, 1999.
Mobile communication designs
S. Joshi, R.C.C. Cheung, P. Monajemi, and J.D. Villasenor, “Traffic-based Study of Femtocell Access Policy Impacts on HSPA Service Quality”, to appear in Proceedings of IEEE International Globecom 2009 Communications Quality of Service, Reliability and Performance Modeling Symposium (GC’09 CQRPM), Hawaii, USA, 2009.
Computer Aided Designs (CAD)
C.W. Yu, F. Cox, W. Luk, and R.C.C. Cheung, “Hydrate: Hybrid Reconfigurable Architecture Expressions”, International conference on Field-Programmable Technology (FPT), India, Dec, 2011.
H. Fan, Y.L. Wu, and C.C. Cheung, “Design Automation for Reconfigurable Interconnection Networks”, in Proceedings of the Applied Reconfigurable Computing (ARC), Bangkok, Thailand, 2009.
L. Zhou, C.C. Cheung and Y.L. Wu, “What if Merging Connection and Switch Boxes — an Experimental Revisit on FPGA Architectures”, in Proceedings of International Conference on Communications, Circuits and Systems (ICCCAS), pp. 1295-1299, Vol. 2, June, Chengdu, China, 2004. (received Best Paper Award) | PDF
H. Fan, Y.L. Wu, C.C. Cheung and J. Liu, “On Optimal Irregular Switch Box Designs”, in Proceedings of the IEEE International Conference on Field Programmable Logic and Applications (FPL), LNCS 3203, pp. 189-199, Antwerp, Belgium, 2004. | PDF | Slides
H. Fan, J. Liu, Y.L. Wu, and C.C. Cheung, “On Optimum Designs of Universal Switch Blocks,” in Proceedings of International Conference on Field Programmable Logic and Applications (FPL), LNCS 2438, pp. 142-151, Montpellier, France, 2002. | PDF |Slides
H. Fan, J. Liu, Y.L. Wu, and C.C. Cheung, “On Optimum Switch Box Designs for 2-D FPGAs, in Proceedings of IEEE/ACM Design Automation Conference (DAC), pp. 203-208, Las Vegas, June, 2001. | Slides
Y.L. Wu, H. Fan, W. Wong, K.C. Cheng, and C.C. Cheung, “On Strong Locality Properties of Alternative Wires in Digital Circuits,” in Proceedings of Workshop on Synthesis And System Integration of MIxed technologies (SASIMI), pp. 244-250, Hiroshima, Japan, 2003. | Slides
Y. L. Wu, C.N. Sze, C.C. Cheung and H. Fan, “On Improved Graph-Based Alternative Wiring Scheme for Multi-Level Logic Optimization”, IEEE International Conference in Electronics Circuits and Systems (ICECS), Lebanon, 2000.
C.C. Cheung, Y.L. Wu, and D.I. Cheng, “Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques,” in Proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 233-239, March, Munich, Germany, Mar, 2001. | Slides