CALAS

Our paper  “Parameter space for the architecture of FFT-based Montgomery modular multiplication”  has been accepted for publication in the IEEE Transactions on Computers.  In this paper, a systematic parameter selection method is proposed for efficient FFT-based Montgomery modular multiplication implementation. The architecture prototypes have better performance in terms of latency and area-latency product over the state-of-the-art when the operand sizes are larger than 3000-bit.

Our paper  “Fast and Generic Inversion Architectures over GF(2m) Using Modified Itoh-Tsujii Algorithms”  has been accepted for publication in the IEEE Transactions on Circuits and Systems II. We have proposed in this paper two novel architectures for multiplicative inverse over GF(2^m), which enhance  both  speed and  area-time product  of  the circuits compared with the state-of-arts.

Our paper, “A Fast CU Size Decision Algorithm for HEVC Intra Encoder”, has been accepted  for publication in IEEE Transactions on  Circuits and Systems for Video Technology (TCSVT) which is a top journal in the field of video technology and systems. The accepted paper proposed a fast block partitioning algorithm for High Efficient Video Coding (HEVC) standard.

Mr. Winston DAI’s paper titled “Time-Efficient Computation of Digit Serial Montgomery Multiplication” has been accepted at International Symposium on Integrated Circuits 2014 (ISIC’14). ISIC is recognized as one of the major conferences in the highly important field of theory, design, and implementation of integrated circuits and systems. This year’s conference will be held in Singapore on December 10-12. Congratulations!

Ref: http://www.isic2014.org/

Mr. Benben Liu has received the Research Tuition Scholarship from Chow Yei Ching School of Graduate Studies for his outstanding research performance. The tuition fee for the period from Apr. 2015 to Aug. 2015 will be waived. Congratulations!

Dr. Manish Jaiswal, Mr. Benben Liu, Dr. Zahid Ullar,  and Mr. Edward Xin have been granted the captioned Award in recognition of their outstanding academic performance in their research studies in the last twelve months. Congratulations!

Congratulation for Manish Jaiswal’s successful defense on his PhD thesis titled “Configurable Architectures for Mixed High Precision Floating Point Arithmetic”, on 14th July, 2014.